FCH47N60 ? n-channel mosfet ?2009 fairchild semiconductor corporation FCH47N60 rev. c1 www.fairchildsemi.com 1 may 2013 FCH47N60 n-channel superfet ? mosfet 600 v, 47 a, 70 m ? features ? 650 v att j = 150c ?typ. r ds(on) = 58 m ? ? ultra-low gate charge (typ. q g = 210 nc) ? low effective output capacitance (typ. c oss eff. = 420 pf) ? 100% avalanche tested ? rohs compliant applications ? solar inverter ? ac-dc power supply description the FCH47N60 superfet ? mosfet is fairchild semiconduc- tor?s first generation of high-vo ltage super-junction (sj) mosfet family that utilizes charge- balance technology for outstanding low on-resistance and lower gate charge performance. this tech- nology is tailored to minimize conduction loss and provide supe- rior switching performance, dv/dt rate, and avalanche energy. this superfet mosfet is suitable for the switching power applications such as pfc, server/telecom power, fpd tv power, atx power, and industrial power. mosfet maximum ratings t c = 25c unless otherwise noted* thermal characteristics symbol parameter FCH47N60_f133 unit v dss drain to source voltage 600 v i d drain current continuous (t c = 25c) 47 a continuous (t c = 100c) 29.7 i dm drain current pulsed (note 1) 141 a v gss gate to source voltage 30 v e as single pulsed avalanche energy (note 2) 1800 mj i ar avalanche current (note 1) 47 a e ar repetitive avalanche energy (note 1) 41.7 mj dv/dt peak diode recovery dv/dt (note 3) 4.5 v/ns p d power dissipation (t c = 25c) 417 w derate above 25c 3.33 w/c t j , t stg operating and storage temperature range -55 to +150 c t l maximum lead temperature for soldering purpose, 1/8? from case for 5 seconds 300 c symbol parameter typ. max. unit r ? jc thermal resistance, junction to case, maximum 0.3 c/w r ? ja thermal resistance, case-to-sink 0.24 c/w r ? ja thermal resistance, junction to ambient, maximum 41.7 c/w *drain current limited by maximum junction temperature. g s d to-247 d g s
FCH47N60 ? n-channel mosfet ?2009 fairchild semiconductor corporation FCH47N60 rev. c1 www.fairchildsemi.com 2 package marking and ordering information electrical characteristics t c = 25c unless otherwise noted. off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics device marking device package reel size tape width quantity FCH47N60 FCH47N60_f133 to-247 30 symbol parameter test conditions min. typ. max. unit bv dss drain-to-source breakdown voltage v gs = 0 v, i d = 250 a, t c = 25c 600 v v gs = 0 v, i d = 250 a, t c = 150c 650 v ? bv dss ? t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25c 0.6 v/c bv ds drain-source avalanche breakdown voltage v gs = 0 v, i d = 47 a 700 v i dss zero gate voltage drain current v ds = 600 v, v gs = 0 v 1 ? a v ds = 480 v, t c = 125c 10 i gss gate-to-body leakage current v gs = 30 v, v ds = 0 v 100 na v gs(th) gate threshold voltage v gs = v ds , i d = 250 ? a3.0 5.0v r ds(on) static drain-to-source on resistance v gs = 10 v, i d = 23.5 a 0.058 0.070 ? g fs forward transconductance v ds = 40 v, i d = 23.5 a (note 4) 40 s c iss input capacitance v ds = 25 v, v gs = 0 v f = 1.0 mhz 5900 8000 pf c oss output capacitance 3200 4200 pf c rss reverse transfer capacitance 250 pf c oss output capacitance v ds = 480 v, v gs = 0 v, f = 1.0 mhz 160 pf c oss eff. effective output capacitance v ds = 0 v to 400 v, v gs = 0 v 420 pf t d(on) turn-on delay v dd = 300 v, i d = 47 a r g = 25 ? (note 4, 5) 185 430 ns t r turn-on rise time 210 450 ns t d(off) turn-off delay 520 1100 ns t f turn-off fall time 75 160 ns q g(tot) total gate charge at 10 v v ds = 480 v, i d = 47 a, v gs = 10 v (note 4, 5) 210 270 nc q gs gate to source gate charge 38 nc q gd gate to drain ?miller? charge 110 nc i s maximum continuous drain-to-source diode forward current 47 a i sm maximum pulsed drain-to-source diode forward current 141 a v sd drain-to-source diode forward voltage v gs = 0 v, i sd = 47 a 1.4 v t rr reverse-recovery time v gs = 0 v, i sd = 47 a di f /dt = 100 a/ ? s (note 4) 590 ns q rr reverse-recovery charge 25 ? c notes: 1. repetitive rating: pulse width limit ed by maximum junction temperature. 2. i as = 18 a, v dd = 50 v, r g = 25 ? , starting t j = 25 ? c. 3. i sd ? 47 a, di/dt ? 200 a/ ? s, v dd ? bv dss , starting t j = 25 ? c. 4. pulse test: pulse width ? 300 ? s, duty cycle ? 2%. 5. essentially independent of operating temperature typical characteristics.
FCH47N60 ? n-channel mosfet ?2009 fairchild semiconductor corporation FCH47N60 rev. c1 www.fairchildsemi.com 3 typical performance characteristics figure 1. on-region characteristics fi gure 2. transfer characteristics figure 3. on-resistance variation vs. figure 4. body diode forward voltage drain current and gate voltage v ariation vs. s ource current and temperature figure 5. capacitance characteristics figure 6. gate charge characteristics 10 -1 10 0 10 1 10 0 10 1 10 2 v gs top : 15.0 v 10.0 v 8.0 v 7.0 v 6.5 v 6.0 v bottom : 5.5 v notes : 1. 250 s pulse test 2. t c = 25 i d , drain current [a] v ds , drain-source voltage [v] 246810 10 0 10 1 10 2 note 1. v ds = 40v 2. 250 s pulse test -55 150 25 i d , drain current [a] v gs , gate-source voltage [v] 0 20 40 60 80 100 120 140 160 180 200 0.00 0.05 0.10 0.15 0.20 v gs = 20v v gs = 10v note : t j = 25 r ds(on) [ ? ],drain-source on-resistance i d , drain current [a] 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 10 0 10 1 10 2 25 150 notes : 1. v gs = 0v 2. 250 s pulse test i dr , reverse drain current [a] v sd , source-drain voltage [v] 10 -1 10 0 10 1 0 5000 10000 15000 20000 25000 30000 c iss = c gs + c gd (c ds = shorted) c oss = c ds + c gd c rss = c gd notes : 1. v gs = 0 v 2. f = 1 mhz c rss c oss c iss capacitance [pf] v ds , drain-source voltage [v] 0 50 100 150 200 250 0 2 4 6 8 10 12 v ds = 250v v ds = 100v v ds = 400v note : i d = 47a v gs , gate-source voltage [v] q g , total gate charge [nc]
FCH47N60 ? n-channel mosfet ?2009 fairchild semiconductor corporation FCH47N60 rev. c1 www.fairchildsemi.com 4 typical performance characteristics (continued) figure 7. breakdown voltage variation figure 8. on-resistance variation vs. temperature vs. temperature figure 9. safe operating area figure 10. maximum drain current vs. case temperature figure 11. transient thermal response curve -100 -50 0 50 100 150 200 0.8 0.9 1.0 1.1 1.2 notes : 1. v gs = 0 v 2. i d = 250 a bv dss , (normalized) drain-source breakdown voltage t j , junction temperature [ o c] -100 -50 0 50 100 150 200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 notes : 1. v gs = 10 v 2. i d = 47 a r ds(on) , (normalized) drain-source on-resistance t j , junction temperature [ o c] 10 0 10 1 10 2 10 3 10 -2 10 -1 10 0 10 1 10 2 operation in this area is limited by r ds(on) dc 10 ms 1 ms 100 us notes : 1. t c = 25 o c 2. t j = 150 o c 3. single pulse i d , drain current [a] v ds , drain-source voltage [v] 25 50 75 100 125 150 0 10 20 30 40 50 i d , drain current [a] t c , case temperature [ ] 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -2 10 -1 notes : 1. z jc (t) = 0.3 /w max. 2. d uty f actor, d =t 1 /t 2 3. t jm - t c = p dm * z jc (t) single pulse d=0.5 0.02 0.2 0.05 0.1 0.01 z jc (t), thermal response t 1 , square w ave pulse duration [sec] t 1 p dm t 2
FCH47N60 ? n-channel mosfet ?2009 fairchild semiconductor corporation FCH47N60 rev. c1 www.fairchildsemi.com 5 figure 12. gate charge test circuit & waveform figure 13. resistive switching test circuit & waveforms figure 14. unclamped inductive sw itching test circuit & waveforms
FCH47N60 ? n-channel mosfet ?2009 fairchild semiconductor corporation FCH47N60 rev. c1 www.fairchildsemi.com 6 figure 15. peak diode recovery dv/dt test circuit & waveforms
FCH47N60 ? n-channel mosfet ?2009 fairchild semiconductor corporation FCH47N60 rev. c1 www.fairchildsemi.com 7 physical dimensions figure 16. to-247, molded, 3-lead, jedec variation ab package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specif- ically the warranty therein, which covers fairchild products. always visit fairchild semiconducto r?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/package/p ackagedetails.html?id=pn_to247-003
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